WM8310GEB/V Wolfson Microelectronics, WM8310GEB/V Datasheet - Page 130

• Manufacturer Part Number: WM8310GEB/V
• Description: POWER MANAGEMENT SUBSYSTEM, 169BGA
• Manufacturer: Wolfson Microelectronics

Specifications of WM8310GEB/V

• Supply Voltage: 7V
• No. Of Step-down Dc - Dc Converters: 4
• No. Of Ldo Regulators: 11
• Digital Ic Case Style: BGA
• No. Of Pins: 169
• No. Of Regulated Outputs: 13
• Operating Temperature Range: -40°C To
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

WM8310
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Table 73 List of GPIO Input Functions
Further details of the GPIO input de-bounce time are noted in Section 21.3.
GPn_FN
GPn_FN
Ah
Bh
Ch
Dh
Eh
Ah
Bh
Fh
0h
1h
2h
3h
4h
8h
9h
Hardware
Enable 1
Hardware
Enable 2
Hardware
Control input 1
Hardware
Control input 2
Hardware
Control input 1
Hardware
Control input 2
GPIO
Oscillator clock
ON state
SLEEP state
Power State
Change
DC-DC1 DVS
Done
DC-DC2 DVS
Done
External Power
Enable 1
External Power
Enable 2
GPIO OUTPUT
GPIO INPUT
FUNCTION
FUNCTION
Control input for enabling one or more DC
Converters and LDO Regulators.
See Section 15.
Control input for enabling one or more DC
Converters and LDO Regulators.
See Section 15.
Control input for selecting the operating mode
and/or output voltage of one or more DC
Converters and LDO Regulators.
See Section 15.
Control input for selecting the operating mode
and/or output voltage of one or more DC
Converters and LDO Regulators.
See Section 15.
Control input for selecting the operating mode
and/or output voltage of one or more DC
Converters and LDO Regulators.
See Section 15.
Control input for selecting the operating mode
and/or output voltage of one or more DC
Converters and LDO Regulators.
See Section 15.
GPIO output. Logic level is set by writing to the GPn_LVL
register bits. See Section 21.3.
32.768kHz clock output. See Section 13.
Logic output indicating that the WM8310 is in the ON state. See
Section 11.5.
Logic output indicating that the WM8310 is in the SLEEP state.
See Section 11.5.
Logic output asserted whenever a Power On Reset, or an ON,
OFF, SLEEP or WAKE transition has completed.
Under default polarity (GPn_POL=1), the logic level is the same
as the PS_INT interrupt status flag. Note that, if any of the
associated Secondary interrupts is masked, then the respective
event will not affect the Power State Change GPIO output.
See Section 11.2 and Section 11.4.
Logic output indicating that DC-DC1 Buck converter DVS slew
has been completed. This signal is temporarily de-asserted
during voltage transitions (including non-DVS transitions). See
Section 15.6.
Logic output indicating that DC-DC1 Buck converter DVS slew
has been completed. This signal is temporarily de-asserted
during voltage transitions (including non-DVS transitions). See
Section 15.6.
Logic output assigned to one of the timeslots in the ON/OFF
and SLEEP/WAKE sequences. This can be used for
sequenced control of external circuits. See Section 15.3.
Logic output assigned to one of the timeslots in the ON/OFF
and SLEEP/WAKE sequences. This can be used for
sequenced control of external circuits. See Section 15.3.
DESCRIPTION
DESCRIPTION
PP, December 2009, Rev 3.0
32ms to 64ms
32ms to 64ms
DE-BOUNCE
32μs to 64μs
32μs to 64μs
32μs to 64μs
32μs to 64μs
Pre-Production
TIME
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