WM8310GEB/V Wolfson Microelectronics, WM8310GEB/V Datasheet - Page 60

• Manufacturer Part Number: WM8310GEB/V
• Description: POWER MANAGEMENT SUBSYSTEM, 169BGA
• Manufacturer: Wolfson Microelectronics

Specifications of WM8310GEB/V

• Supply Voltage: 7V
• No. Of Step-down Dc - Dc Converters: 4
• No. Of Ldo Regulators: 11
• Digital Ic Case Style: BGA
• No. Of Pins: 169
• No. Of Regulated Outputs: 13
• Operating Temperature Range: -40°C To
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

WM8310
14.5 OTP / DBE INTERRUPTS
14.6 DORW MEMORY CONTENTS
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Table 27 OTP Memory Control
The OTP and DBE memories are associated with two Interrupt event flags.
The OTP_CMD_END_EINT interrupt is set each time an OTP / DBE Command has completed or if
OTP Auto-Program has completed. (See Section 14.4 for a definition of the OTP and DBE
Commands. See Section 14.6.3 for details of the OTP Auto-Program function.)
The OTP_ERR_EINT interrupt is set when an OTP / DBE Error has occurred. The errors detected
include DBE Read Failure, OTP Verify Failure and attempted OTP Write to a page that has been
Finalised.
Each of these secondary interrupts triggers a primary OTP Memory Interrupt, OTP_INT (see
Section 23). This can be masked by setting the mask bit(s) as described in Table 71.
R16402
(4012h)
Interrupt Status
2
R16410
(401Ah)
Interrupt Status
2 Mask
Table 28 OTP Memory Interrupts
The DORW is the DBE/OTP Register Window, as described in Section 14.2. Under normal operating
conditions, this memory area is initialised with data from the integrated OTP or an external DBE
memory. The DORW memory addresses range from R30720 (7800h) to R30759 (7827h). The
complete register map definition is described in Section 28.
The register fields in the DORW allow the start-up configuration of the DC-DC Converters, the LDO
Regulators, GPIO pins 1-6 and Status LED outputs to be programmed. The DORW also provides
control of the Battery Charger, Clocking, USB Current Limit and the Start-Up (SYSOK) voltage
threshold.
Most of the DORW contents are duplicates of control registers that exist in the main register area
below the DORW addresses. In theses cases, reading or writing to either address will have the same
effect.
Some register fields are defined only in the DORW area; a detailed description of these fields is
provided in the following sub-sections.
ADDRESS
ADDRESS
BIT
BIT
5
4
5
4
OTP_CMD_END_EINT
OTP_ERR_EINT
IM_OTP_CMD_END_EINT
IM_OTP_ERR_EINT
LABEL
LABEL
DEFAULT
OTP / DBE Command End interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
OTP / DBE Command Fail interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
If DBE is selected (OTP_MEM = 0):
00 = Page 2
01 = Page 3
10 = Page 4
11 = Reserved
PP, December 2009, Rev 3.0
DESCRIPTION
DESCRIPTION
Pre-Production
60