WM8310GEB/V Wolfson Microelectronics, WM8310GEB/V Datasheet - Page 132

• Manufacturer Part Number: WM8310GEB/V
• Description: POWER MANAGEMENT SUBSYSTEM, 169BGA
• Manufacturer: Wolfson Microelectronics

Specifications of WM8310GEB/V

• Supply Voltage: 7V
• No. Of Step-down Dc - Dc Converters: 4
• No. Of Ldo Regulators: 11
• Digital Ic Case Style: BGA
• No. Of Pins: 169
• No. Of Regulated Outputs: 13
• Operating Temperature Range: -40°C To
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

WM8310
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Table 75 GPIO Pin Configuration
When the GPIO output function is selected (GPn_FN = 0h, GPn_DIR = 0), the state of a GPIO
output is controlled by writing to the corresponding GPn_LVL register bit, as defined in Table 76.
The logic level of a GPIO input is determined by reading the corresponding GPn_LVL register bit. If
GPn_POL is set, then the read value of the GPn_LVL field for a GPIO input is the inverse of the
external signal. Note that, when the GPIO input level changes, the logic level of GPn_LVL will only be
updated after the maximum de-bounce period, as listed in Table 73. An input pulse that is shorter
than the minimum de-bounce period will be filtered by the de-bounce function and will be ignored.
If a GPIO is configured as a CMOS output (ie. GPn_OD = 0), then the read value of the GPn_LVL
field will indicate the logic level of that output. If GPn_POL is set, then the read value of the
GPn_LVL field for a GPIO output is the inverse of the level on the external pad.
If a GPIO is configured as an Open Drain output, then the read value of GPn_LVL is only valid when
the internal pull-up resistor is enabled on the pin (ie. when GPn_PULL = 10). The read value is also
affected by the GPn_POL bit, as described above for the CMOS case.
If a GPIO is tri-stated (GPn_ENA = 0), then the read value of the corresponding GPn_LVL field is
invalid.
R16440
(4038h)
to
R16451
(4043h)
Note: n is a number between 1 and 12 that identifies the individual GPIO.
R16396
(400Ch)
GPIO Level
ADDRESS
ADDRESS
14:13
BIT
BIT
3:0
11
10
15
12
11
10
9
8
7
6
9
7
GPn_DIR
GPn_PULL
[1:0]
GPn_INT_M
ODE
GPn_PWR_
DOM
GPn_POL
GPn_OD
GPn_ENA
GPn_FN [3:0]
GP12_LVL
GP11_LVL
GP10_LVL
GP9_LVL
GP8_LVL
GP7_LVL
LABEL
LABEL
DEFAULT
DEFAULT
0000
01
1
0
0
1
0
0
0
0
0
0
0
0
GPIOn pin direction
0 = Output
1 = Input
GPIOn Pull-Up / Pull-Down
configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
GPIOn Interrupt Mode
0 = GPIO interrupt is rising edge
triggered (if GPn_POL=1) or falling
edge triggered (if GPn_POL =0)
1 = GPIO interrupt is triggered on
rising and falling edges
GPIOn Power Domain
See Table 77.
GPIOn Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
GPIOn Output pin configuration
0 = CMOS
1 = Open Drain
GPIOn Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
GPIOn Pin Function
See Table 78.
GPIOn level.
When GPn_FN = 0h and GPn_DIR
= 0, write to this bit to set a GPIO
output.
Read from this bit to read GPIO
input level.
PP, December 2009, Rev 3.0
DESCRIPTION
DESCRIPTION
Pre-Production
132