WM8310GEB/V Wolfson Microelectronics, WM8310GEB/V Datasheet - Page 141

• Manufacturer Part Number: WM8310GEB/V
• Description: POWER MANAGEMENT SUBSYSTEM, 169BGA
• Manufacturer: Wolfson Microelectronics

Specifications of WM8310GEB/V

• Supply Voltage: 7V
• No. Of Step-down Dc - Dc Converters: 4
• No. Of Ldo Regulators: 11
• Digital Ic Case Style: BGA
• No. Of Pins: 169
• No. Of Regulated Outputs: 13
• Operating Temperature Range: -40°C To
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Pre-Production
Figure 29 Interrupt Logic
23.1 PRIMARY INTERRUPTS
w
The interrupt logic is illustrated in Figure 29.
Following the assertion of the IRQ
determine which primary interrupt caused the event by reading the primary interrupt register R16400
(4010h). This register is defined in Section 23.1.
After reading the primary interrupt register, the host processor must read the corresponding
secondary interrupt register(s) in order to determine which specific event caused the IRQ
asserted. The host processor clears the secondary interrupt bit by writing a logic 1 to that bit.
The primary interrupts are defined in Table 86. These bits are Read Only. They are set when any of
the associated unmasked secondary interrupts is set. They can only be reset when all of the
associated secondary resets are cleared or masked.
Each primary interrupt can be masked. When a mask bit is set, the corresponding primary interrupt is
masked and does not cause the IRQ
are valid regardless of whether the mask bit is set. The primary interrupts are all masked by default.
R16400
(4010h)
System
Interrupts
ADDRESS
BIT
15
14
13
12
11
8
7
PS_INT
TEMP_INT
GP_INT
ON_PIN_INT
WDOG_INT
AUXADC_INT
PPM_INT
¯ ¯ ¯ pin to be asserted. The primary interrupt bits in R16408 (4018h)
¯ ¯ ¯ pin to indicate an Interrupt event, the host processor can
LABEL
Power State primary interrupt
0 = No interrupt
1 = Interrupt is asserted
Thermal primary interrupt
0 = No interrupt
1 = Interrupt is asserted
GPIO primary interrupt
0 = No interrupt
1 = Interrupt is asserted
ON Pin primary interrupt
0 = No interrupt
1 = Interrupt is asserted
Watchdog primary interrupt
0 = No interrupt
1 = Interrupt is asserted
AUXADC primary interrupt
0 = No interrupt
1 = Interrupt is asserted
Power Path Management primary interrupt
0 = No interrupt
PP, December 2009, Rev 3.0
DESCRIPTION
¯ ¯ ¯ pin to be
WM8310
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