WM8310GEB/V Wolfson Microelectronics, WM8310GEB/V Datasheet - Page 131

• Manufacturer Part Number: WM8310GEB/V
• Description: POWER MANAGEMENT SUBSYSTEM, 169BGA
• Manufacturer: Wolfson Microelectronics

Specifications of WM8310GEB/V

• Supply Voltage: 7V
• No. Of Step-down Dc - Dc Converters: 4
• No. Of Ldo Regulators: 11
• Digital Ic Case Style: BGA
• No. Of Pins: 169
• No. Of Regulated Outputs: 13
• Operating Temperature Range: -40°C To
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Pre-Production
21.3 CONFIGURING GPIO PINS
w
Table 74 List of GPIO Output Functions
The GPIO pins are configured using the Resister fields defined in Table 75.
The function of each GPIO is selected using the GPn_FN register field. The pin direction field
GPn_DIR selects between input functions and output functions. See Section 21.2 for a summary of
the available GPIO functions.
The polarity of each GPIO can be configured using the GPn_POL bits. This inversion is effective
both on GPIO inputs and outputs. When GPn_POL = 1, the non-inverted ‘Active High’ polarity
applies. The opposite logic can be selected by setting GPn_POL = 0.
The voltage power domain of each GPIO is determined by the GPn_PWR_DOM register. Note that
the available options vary between different GPIO pins, as described in Table 77.
A GPIO output may be either CMOS driven or Open Drain. This is selected using the GPn_OD bits.
Internal pull-up or pull-down resistors can be enabled on each pin using the GPn_PULL field. Both
resistors are available for use when the associated GPIO is an input. When the GPIO pin is
configured as an Open Drain output, the internal pull-up resistor may be required if no external pull-
up resistors are present.
The GPIO pins may be enabled or tri-stated using the GPn_ENA register field. When GPn_ENA = 0,
the respective pin is tri-stated. A tri-stated pin exhibits high impedance to any external circuit and is
disconnected from the internal GPIO circuits. The pull-up and pull-down resistors are disabled when
a GPIO pin is tri-stated.
GPIO pins can generate an interrupt (see Section 21.4). The GPn_INT_MODE field selects whether
the interrupt occurs on a single edge only, or else on both rising and falling edges. When single edge
is selected, the active edge is the rising edge (when GPn_POL = 1) or the falling edge (when
GPn_POL = 0.
GPn_FN
Ch
Dh
Eh
Fh
System Supply
Good (SYSVDD
Good)
Converter Power
Good
(PWR_GOOD)
External Power
Clock
Auxiliary Reset
GPIO OUTPUT
FUNCTION
Logic output from SYSVDD monitoring circuit. This function
represents the internal SYSOK signal. See Section 24.4.
Status output indicating that all selected DC Converters and
LDO Regulators are operating correctly. Only asserted in ON
and SLEEP modes. See Section 15.14.
2MHz clock output suitable for clocking external DC-DC
Converters. This clock signal is synchronized with the WM8310
DC Converters clocking signal. See Section 13.
Logic output indicating a Reset condition. This signal is
asserted in the OFF state. The status in SLEEP mode is
configurable. See Section 11.7.
Note that the default polarity for this function (GPn_POL=1) is
“Active High”. Setting GPn_POL=0 will select “Active Low”
function.
DESCRIPTION
PP, December 2009, Rev 3.0
WM8310
131