WM8310GEB/V Wolfson Microelectronics, WM8310GEB/V Datasheet - Page 147

• Manufacturer Part Number: WM8310GEB/V
• Description: POWER MANAGEMENT SUBSYSTEM, 169BGA
• Manufacturer: Wolfson Microelectronics

Specifications of WM8310GEB/V

• Supply Voltage: 7V
• No. Of Step-down Dc - Dc Converters: 4
• No. Of Ldo Regulators: 11
• Digital Ic Case Style: BGA
• No. Of Pins: 169
• No. Of Regulated Outputs: 13
• Operating Temperature Range: -40°C To
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Pre-Production
w
R16402
(4012h)
Interrupt Status
2
R16410
(401Ah)
Interrupt Status
2 Mask
Table 94 Current Sink Interrupts
23.2.11 REAL TIME CLOCK INTERRUPTS
The primary RTC_INT interrupt comprises two secondary interrupts as described in Section 20.3.
The secondary interrupt bits are defined in Table 95.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a RTC_INT interrupt. The secondary interrupt bits in R16401
(4011h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked
by default.
R16401
(4011h)
Interrupt Status
1
R16409
(4019h)
Interrupt Status
1 Mask
Table 95 Real Time Clock (RTC) Interrupts
23.2.12 OTP MEMORY INTERRUPTS
The primary OTP_INT interrupt comprises two secondary interrupts as described in Section 14.5.
The secondary interrupt bits are defined in Table 96.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a OTP_INT interrupt. The secondary interrupt bits in R16402
(4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked
by default.
ADDRESS
ADDRESS
BIT
BIT
7
6
7
6
3
2
3
2
CS2_EINT
CS1_EINT
IM_CS2_EINT
IM_CS1_EINT
RTC_PER_EINT
RTC_ALM_EINT
IM_RTC_PER_EINT
IM_RTC_ALM_EINT
LABEL
LABEL
Current Sink 2 interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
Current Sink 1 interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
RTC Periodic interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
RTC Alarm interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
PP, December 2009, Rev 3.0
DESCRIPTION
DESCRIPTION
WM8310
147