WM8310GEB/V Wolfson Microelectronics, WM8310GEB/V Datasheet - Page 145

• Manufacturer Part Number: WM8310GEB/V
• Description: POWER MANAGEMENT SUBSYSTEM, 169BGA
• Manufacturer: Wolfson Microelectronics

Specifications of WM8310GEB/V

• Supply Voltage: 7V
• No. Of Step-down Dc - Dc Converters: 4
• No. Of Ldo Regulators: 11
• Digital Ic Case Style: BGA
• No. Of Pins: 169
• No. Of Regulated Outputs: 13
• Operating Temperature Range: -40°C To
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Pre-Production
w
R16401
(4011h)
Interrupt Status
1
R16409
(4019h)
Interrupt Status
1 Mask
Table 90 ON Pin Interrupt
23.2.5
The primary WDOG_INT interrupt comprises a single secondary interrupt as described in Section 25.
The secondary interrupt bits are defined in Table 91.
The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event
is masked and does not trigger a WDOG_INT interrupt. The secondary interrupt bit in R16401
(4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by
default.
R16401
(4011h)
Interrupt Status
1
R16409
(4019h)
Interrupt Status
1 Mask
Table 91 Watchdog Timer Interrupts
23.2.6
23.2.7
23.2.8
The primary AUXADC_INT interrupt comprises five secondary interrupts as described in
Section 18.5. The secondary interrupt bits are defined in Table 92.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a AUXADC_INT interrupt. The secondary interrupt bits in
R16401 (4011h) are valid regardless of whether the mask bit is set. The secondary interrupts are all
masked by default.
R16401
(4011h)
Interrupt Status
1
R16409
(4019h)
Interrupt Status
1 Mask
ADDRESS
ADDRESS
ADDRESS
WATCHDOG INTERRUPTS
RESERVED
RESERVED
AUXADC INTERRUPTS
BIT
BIT
BIT
7:4
12
12
11
11
8
8
ON_PIN_CINT
IM_ON_PIN_CINT
WDOG_TO_EINT
IM_WDOG_TO_EINT
AUXADC_DATA_EINT
AUXADC_DCOMPn_EINT
IM_AUXADC_DATA_EINT
LABEL
LABEL
LABEL
ON pin interrupt.
(Rising and Falling Edge triggered)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Watchdog timeout interrupt.
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
AUXADC Data Ready interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
AUXADC Digital Comparator n interrupt
(Trigger is controlled by DCMPn_GT)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
PP, December 2009, Rev 3.0
DESCRIPTION
DESCRIPTION
DESCRIPTION
WM8310
145