PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 174

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3.4
Initially, the CPU should bring the transmitter and receiver to a defined state by issuing
a XRES (transmitter reset) and RHR (receiver reset) command via the CMDRB register.
If data reception should be performed, the receiver must be activated by setting the RAC
bit in MODEB to 1.
After having performed the initialization, the CPU switches each individual B-channel of
the IPAC into operational phase by setting the PU bit in the CCR1 register (power-up).
Now the IPAC is ready to transmit and receive B-Channel data. The control of the data
transfer phase is mainly done by commands from CPU to IPAC via the CMDRB register,
and by interrupt indications from IPAC to CPU.
Additional status information, which does not trigger an interrupt, is available in the
STARB register.
3.4.1
Interrupt Mode
In transmit direction 2
channel. After checking the XFIFOB status by polling the Transmit FIFO Write Enable bit
(XFW in STARB register) or after a Transmit Pool Ready (XPR) interrupt, up to 64 bytes
may be entered by the CPU to the XFIFOB.
The transmission of a frame can then be started issuing a XTF command via the CMDRB
register. If the transmit command does not include an end of message indication
(CMDRB : XME), the IPAC will repeatedly request for the next data block by means of a
XPR interrupt as soon as no more than 64 bytes are stored in the XFIFOB, i.e. a 64-byte
pool is accessible to the CPU.
This process will be repeated until the CPU indicates the end of message per command,
after which frame transmission is finished correctly by appending the CRC and closing
flag sequence.
In case no more data is available in the XFIFOB prior to the arrival of XME, the
transmission of the frame is terminated with an abort sequence and the CPU is notified
per interrupt (EXIRB : XDU). The frame may also be aborted per software
(CMDRB : XRES).
Semiconductor Group
B-Channel Data Transfer
Data Transmission
64 byte FIFO buffers (transmit pools) are provided for each
174
Operational Description
PSB 2115
PSF 2115
11.97