PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 230

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Non-auto mode,
2-byte address
Transparent
mode 1
Transparent
mode 0
4.2.15
Value after reset: (not defined)
RHCRB
Value of the HDLC control field corresponds to the last received frame.
Note: RHCRB is duplicated into RFIFOB for every frame.
Mode
Non-auto mode,
1-byte address
4.2.16
Value after reset: (not defined)
XBCL
Together with XBCH (bits XBC11 ... XBC8) this register is used in DMA mode only, to
program the length (1 ... 4095 bytes) of the next frame to be transmitted.
This allows the IPAC to request the correct amount of DMA cycles after an XTF
command via CMDRB.
Semiconductor Group
RHCRB - Receive HDLC Control Register for B-Channel (READ)
7
XBCL - Transmit Byte Count Low (WRITE)
7
XBC7
RHCR
230
Contents of RHCR
2
3
3
2
nd
rd
rd
nd
byte after flag
byte after flag
byte after flag
byte after flag
Detailed Register Description
0
0
XBC0
PSB 2115
PSF 2115
(2A/6A)
(29/69)
11.97