PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 178

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

The activities during frame transmission (supposed two frames, 36 bytes and 104 bytes)
is shown in figure 83.
Figure 83
DMA Mode
Prior to data transmission, the length of the next frame to be transmitted must be
programmed via the Transmit Byte Count Registers (XBCH, XBCL). The resulting byte
count equals the programmed value plus one byte, i.e. since 12 bits are provided via
XBCH, XBCL (XBC11. . .XBC0) a frame length of 1 up to 4096 bytes (4 Kbytes) can be
selected.
After this, data transmission can be initiated by command (XTF). The IPAC will then
autonomously request the correct amount of write bus cycles by activating the DRQTA/
B line. Depending on the programmed frame length, block data transfers of
n
are requested everytime a 64-byte FIFO half (transmit pool) is empty and accessible to
the DMA controller.
Semiconductor Group
Serial
Interface
IPAC
CPU
Interface
64-bytes + remainder (n = 0, 1,…64)
36 Bytes
Continuous Frames Transmission Sequence Example
WR
...
ITF
XTF
XPR
XME
36 Bytes
Frame 1
64 Bytes
WR
...
XTF
178
XPR
40 Bytes
64 Bytes
WR
...
XTF
Frame 2
XPR
Operational Description
XTF + XME
40 Bytes
PSB 2115
PSF 2115
XPR
ITD09650
ITF
11.97