PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 235
PSB2115FV1.2D
Manufacturer Part Number
PSB2115FV1.2D
Description
Manufacturer
Lantiq
Datasheet
1.PSB2115FV1.2D.pdf
(317 pages)
Specifications of PSB2115FV1.2D
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Semiconductor Group
4.2.23
Value after reset: (not defined)
TSAR
TSNR … Time-Slot Number Receive
Defines one of up to 64 possible time-slots (00
number of bits per time-slot can be programmed via RCCR.
RCS2, RCS1 … Receive Clock Shift, Bit 2-1
Together with bit RCS0 in CCR2, the receive clock shift can be adjusted.
4.2.24
Value after reset: 00
XCCR
XBC7 … XBC0 … Transmit Bit Count, Bit 7-0
Defines the number of bits to be transmitted with a time-slot:
Number of bits = XBC + 1. (1 … 256 bits/time-slot)
4.2.25
Value after reset: 00
RCCR
RBC7 … RBC0 … Receive Bit Count, Bit 7-0
Defines the number of bits to be transmitted with a time-slot:
Number of bits = RBC + 1. (1 … 256 bits/time-slot)
7
TSAR - Time-Slot Assignment Register Receive (WRITE)
7
XCCR - Transmit Channel Capacity Register (WRITE)
7
RCCR - Receive Channel Capacity Register (WRITE)
RBC7
XBC7
H
H
TSNR
235
H
–
3F
H
Detailed Register Description
) in which data is received. The
RCS2 RCS1
0
0
0
RBC0
XBC0
PSB 2115
PSF 2115
(33/73)
(31/71)
(32/72)
11.97
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