PSB21383HV1.3XT Infineon Technologies, PSB21383HV1.3XT Datasheet - Page 112
PSB21383HV1.3XT
Manufacturer Part Number
PSB21383HV1.3XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21383HV1.3XT.pdf
(270 pages)
Specifications of PSB21383HV1.3XT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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Data Sheet
3.2.1.2
If parts of a frame get lost because the receive FIFO is full, the Receive Data Overflow
(RDO) byte in the RSTA byte will be set. If a complete frame is lost, i.e. if the FIFO is full
when a new frame is received, the receiver will assert a Receive Frame Overflow (RFO)
interrupt.
The microcontroller sees a cyclic buffer, i.e. if it tries to read more data than available, it
reads the same data again and again. On the other hand, if it doesn’t read or doesn’t
want to read all data, they are deleted anyway after the RMC command.
If the microcontroller reads data without a prior RME or RPF interrupt, the read data is
undefined but the content of the RFIFO would not be corrupted.
Possible Error Conditions during Reception of Frames
102
HDLC Controller
PSB 21381/2
PSB 21383/4
2001-03-12
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