PSB21383HV1.3XT Infineon Technologies, PSB21383HV1.3XT Datasheet - Page 209
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
PSB21383HV1.3XT
Manufacturer Part Number
PSB21383HV1.3XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21383HV1.3XT.pdf
(270 pages)
Specifications of PSB21383HV1.3XT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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7.2.4
Value after reset: 00
TR_
STA
RINF
00: Received INFO 0
01: Received any signal except INFO 2 or INFO 4
10: Received INFO 2
11: Received INFO 4
FECV
0: No illegal code violation detected
1: An illegal code violation according to ANSI T1.605 (far-end-code-violation) was
FSYN
0: The S/T receiver has not yet synchronized or has lost synchronization
1: The S/T receiver has synchronized
LD
0: No receive signal has been detected on the line
1: Any receive signal has been detected on the line
Data Sheet
detected
TR_STA - Transceiver Status Register
7
RINF
... Receiver INFO
... Far-End-Code-Violation
... Frame Synchronization State
... Level Detected
H
0
FECV
199
0
FSYN
Detailed Register Description
0
0
LD
PSB 21381/2
PSB 21383/4
2001-03-12
RD (33
H
)
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