PSB21383HV1.3XT Infineon Technologies, PSB21383HV1.3XT Datasheet - Page 52
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PSB21383HV1.3XT
Manufacturer Part Number
PSB21383HV1.3XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21383HV1.3XT.pdf
(270 pages)
Specifications of PSB21383HV1.3XT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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Data Sheet
2.2.2.1.2 Monitoring Data
Figure 24 gives an example for monitoring of two IOM-2 time slots each on DU or DD
simultaneously. For monitoring on DU and/or DD the channel registers with even
numbers (CDA10, CDA20) are assigned to time slots with even numbers TS(2n) and the
channel registers with odd numbers (CDA11, CDA21) are assigned to time slots with odd
numbers TS(2m+1) (n,m = 0...5). The user has to take care of this restriction by
programming the appropriate time slots.
Figure 24
Example for Monitoring Data
2.2.2.1.3 Monitoring TIC Bus
Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be
monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring)
bit in the control registers CRx. The TSDPx0 must be set to 08
or 88
.
a) Monitoring Data
h
for monitoring from DD respectively.
CDA_CR1.
CDA_CR2.
EN_O:
EN_O:
EN_I:
EN_I:
DPS:
DPS:
TSS:
TSS:
CDA20
CDA10
TS(2n)
TS(2n)
’0’
’1’
’0’
’1’
’1’
’0’
42
TS(2m+1)
TS(2m+1)
CDA11
CDA21
’0’
’0’
’1’
’1’
’1’
’0’
h
for monitoring from DU
DD
DU
n,m = 0...5
PSB 21381/2
PSB 21383/4
Interfaces
2001-03-12
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