PSB21383HV1.3XT Infineon Technologies, PSB21383HV1.3XT Datasheet - Page 180
PSB21383HV1.3XT
Manufacturer Part Number
PSB21383HV1.3XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21383HV1.3XT.pdf
(270 pages)
Specifications of PSB21383HV1.3XT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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Data Sheet
5.1
5.1.1
The DPLL only readjusts with each received F/L edge of the S interface.
If the receiver has not yet synchronized the DPLL will adjust in one step.
5.1.2
The S transmit clock is derived from the S receive clock.
5.1.3
Jitter on the MCLK output is directly related to the crystal tolerance. Only clock dividers
are involved.
Figure 90
Clock waveforms
Jitter
Jitter on IOM-2
Jitter on S
Jitter on MCLK
FSC
DCL
BCL
170
Clock Generation
PSB 21381/2
PSB 21383/4
2001-03-12
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