PSB21383HV1.3XT Infineon Technologies, PSB21383HV1.3XT Datasheet - Page 200
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PSB21383HV1.3XT
Manufacturer Part Number
PSB21383HV1.3XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21383HV1.3XT.pdf
(270 pages)
Specifications of PSB21383HV1.3XT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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Data Sheet
RBC11-8
Four most significant bits of the total number of bytes in a received message.
Note: Normally RBCH and RBCL should be read by the microcontroller after an RME-
7.1.14
Value after reset: FF
TEI1
TEI1 ... Terminal Endpoint Identifier
In all message transfer modes except in transparent modes 0, 1 and extended
transparent mode, TEI1 is used for address recognition. In the case of a two-byte
address field, it contains the value of the first programmable Terminal Endpoint Identifier
according to the ISDN LAPD-protocol.
In non-auto-modes with one-byte address field, TEI1 is a command address, according
to X.25 LAPB.
EA
This bit is set to ’1’ according to HDLC/LAPD.
interrupt in order to determine the number of bytes to be read from the RFIFO, and
the total message length. The contents of the registers are valid only after an RME
or RPF interrupt, and remain so until the frame is acknowledged via the RMC bit
or RRES.
TEI1 - TEI1 Register 1
7
... Receive Byte Count
... Address field Extension bit
H
TEI1
190
Detailed Register Description
0
EA
PSB 21381/2
PSB 21383/4
2001-03-12
WR (27
H
)
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