PSB21383HV1.3XT Infineon Technologies, PSB21383HV1.3XT Datasheet - Page 54
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
PSB21383HV1.3XT
Manufacturer Part Number
PSB21383HV1.3XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21383HV1.3XT.pdf
(270 pages)
Specifications of PSB21383HV1.3XT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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Data Sheet
.
Figure 26
Examples for the Synchronous Transfer Interrupt Control with one enabled STIxy
a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled
b) Interrupts for data access to time slot 0 (B1 after reset), STOV interrupt used as flag for "last possible CDA
c) Interrupts for data access to time slot 0 and 1 (B1 and B2 after reset), MSTI.STI10, MSTI.STOV10,
d) Interrupts for data access to time slot 0 (B1 after reset), STOV20 interrupt used as flag for "last possible CDA
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
: STI interrupt generated
: STOV interrupt generated for a not acknowledged STI interrupt
access"; MSTI.STI10 and MSTI.STOV20 enabled
MSTI.STI11 and MSTI.STOV11 enabled
access", STOV10 interrupt used as flag for "CDA access failed"; MSTI.STI10, MSTI.STOV10 and
MSTI.STOV20 enabled
TS11
TS11
TS11
TS11
TS0
TS0
TS0
TS0
10
TS0 TS1
’0’
’0’
10
TS0 TS1
’0’
’1’
10
TS0 TS1
’0’
’0’
10
TS0 TS1
’0’
’0’
TS1 TS2
TS1 TS2
TS1 TS2
TS1 TS2
11
’1’
’1’
11
’1’
’1’
11
’0’
’0’
11
’1’
’1’
TS3
TS3
TS3
TS3
44
TS4
TS4
TS4
TS4
TS5 TS6
TS5 TS6
TS5 TS6
TS5 TS6
21
TS5
’1’
’1’
21
TS5
’1’
’1’
21
TS5
’1’
’1’
21
TS5
’1’
’1’
TS7
TS7
TS7
TS7
TS8
TS8
TS8
TS8
TS9 TS10
TS9 TS10
TS9 TS10
TS9 TS10
PSB 21381/2
PSB 21383/4
TS11
TS11
TS11
TS11
20
TS11
’1’
’1’
20
TS11
’1’
’0’
20
TS11
’1’
’1’
20
TS11
’1’
’0’
Interfaces
2001-03-12
sti_stov.vsd
TS0
TS0
TS0
TS0
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