PSB21383HV1.3XT Infineon Technologies, PSB21383HV1.3XT Datasheet - Page 113
PSB21383HV1.3XT
Manufacturer Part Number
PSB21383HV1.3XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21383HV1.3XT.pdf
(270 pages)
Specifications of PSB21383HV1.3XT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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3.2.1.3
The general procedures for a data reception sequence are outlined in the flow diagram
in figure 62.
Figure 62
Data Reception Procedures
Data Sheet
Data Reception Procedure
*
1)
In case of RME the last byte in RFIFO contains
the receive status information RSTA
N
Read Counter
RD_Count := RFBS
or
RD_Count := RBC
Read RD_Count
bytes from RFIFO
Change Block Size
Write EXMR.RFBS
(optional)
Receive Message
Complete
Write RMC
Message End
Pool Full
Receive
Receive
START
RME
RPF
?
?
N
Y
103
Y
*
1)
RBC = RBCH + RBCL register
RFBS: Refer to EXMR register
Read RBC
RD_Count := RBC
HDLC_Rflow.vsd
HDLC Controller
PSB 21381/2
PSB 21383/4
2001-03-12
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