PSB21383HV1.3XT Infineon Technologies, PSB21383HV1.3XT Datasheet - Page 59
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PSB21383HV1.3XT
Manufacturer Part Number
PSB21383HV1.3XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21383HV1.3XT.pdf
(270 pages)
Specifications of PSB21383HV1.3XT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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2.2.3.2
The strobed IOM bit clock is active during the programmed window (see chapter 7.3.8).
Outside the programmed window a ’0’ is driven. Two examples are shown in figure 30.
Figure 30
Strobed IOM Bit Clock. Register SDS_CONF programmed to 01
Data Sheet
FSC
DD,DU
SDS1
(Example1)
SDS1
(Example2)
Example 1:
Example 2:
Strobed IOM-2 Bit Clock
Setting of SDS1_CR:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
TS0
B1
TS1
B2
MON0
TS2
= ’0
= ’0’
= ’0’
= ’1’
= ’5
= ’1’
= ’1’
= ’0’
D CI0
H
H
TS3
’
’
M
R
M
X
TS4
IC1
TS5
IC2 MON1
49
TS6
CI1
TS7
M
R
M
X
TS8
TS9
TS10
H
or 03
TS11
PSB 21381/2
PSB 21383/4
H
bcl_strobed.vsd
TS0
Interfaces
2001-03-12
TS1
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