PSB21383HV1.3XT Infineon Technologies, PSB21383HV1.3XT Datasheet - Page 91
PSB21383HV1.3XT
Manufacturer Part Number
PSB21383HV1.3XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21383HV1.3XT.pdf
(270 pages)
Specifications of PSB21383HV1.3XT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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Figure 51
State Transition Diagram of the Unconditional Transitions
2.3.7.1.2 States
F3 Pending Deactivation
State after deactivation from the S/T interface by info 0. Note that no activation from the
terminal side is possible starting from this state. A ’DI’ command has to be issued to enter
the state ’Power Down’.
F3 Power Down
The S/T interface is deactivated and the IOM-2 interface is or will be deactivated if the
CFS bit of the MODE1 register is set to “1“. Activation is possible from the S/T interface
and from the IOM-2 interface.
F3 Power Up
The S/T interface is deactivated and the IOM-2 interface is activated, i.e. the clocks are
running.
F4 Pending Activation
The SCOUT transmits info 1 towards the network, waiting for info 2.
F5 Unsynchronized
Any signal except info 2 or 4 detected on the S/T interface.
Data Sheet
1)
Possible reset sources:
C/I command RES
software reset via SRES.RES_TR or
reset from pin RST
TIM
DI
Test Mode i
TMi
it
i
TMi
TMi
*
TIM
DI
TIM
DI
Loop A Activated
Loop A Closed
PU
AIL ARL
i3
i3
i3
ARL
ARL
81
*
*
i3
TIM
DI
RES RES
RESET
i0
Reset
*
1)
PSB 21381/2
PSB 21383/4
statem_te_aloop_s.vsd
Interfaces
2001-03-12
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