PSB21383HV1.3XT Infineon Technologies, PSB21383HV1.3XT Datasheet - Page 223
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
PSB21383HV1.3XT
Manufacturer Part Number
PSB21383HV1.3XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21383HV1.3XT.pdf
(270 pages)
Specifications of PSB21383HV1.3XT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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7.3.6
Value after reset: A0
HCI_CR
DPS_CI1
0: The CI1 data is output on DD and input from DU
1: The CI1 data is output on DU and input from DD
EN_CI1
EN_D
EN_B2H
EN_B1H
0: The HDLC (D, B1, B2) and CI1 data is disabled
1: The HDLC (D, B1, B2) and CI1 data is enabled
7.3.7
Value after reset: 40
MON_CR DPS
DPS
0: The Monitor data is output on DD and input from DU
1: The Monitor data is output on DU and input from DD
EN_MON
0: The Monitor data input and output is disabled
1: The Monitor data input and output is enabled
MCS
00: The MONITOR data is output on MON0
01: The MONITOR data is output on MON1
10: The MONITOR data is output on MON2
11: Not defined
Data Sheet
HCI_CR - Control Register for HDLC and CI1 Data
MON_CR - Control Register Monitor Data
7
DPS_
7
CI1
... Data Port Selection CI1 Data
... Enable CI1 Data
... Enable D-Channel Data
... Enable HDLC B2 Data
... Enable HDLC B1 Data
... Data Port Selection
... Enable Output
... MONITOR Channel Selection
MON
EN_
EN_
H
CI1
H
EN_
D
0
EN_
B2H
0
213
EN_
B1H
0
0
0
Detailed Register Description
0
MCS
0
0
0
PSB 21381/2
PSB 21383/4
RD/WR (52
RD/WR (53
2001-03-12
H
H
)
)
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