PEB2096HV31XT Lantiq, PEB2096HV31XT Datasheet - Page 14

• Manufacturer Part Number: PEB2096HV31XT
• Manufacturer: Lantiq

Specifications of PEB2096HV31XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Data Sheet
•
Figure 2-1
Within a burst, the data rate is 384 kbit/s. The 38-bit frame structure is as shown in
Figure 2-1. The framing bit (LF) is always logical ‘1’. The frame also contains the user
channels (2B + D).
It can readily be seen that in the 250 s burst repetition period, 4 D bits, 16 B1 bits and
16 B2 bits are transferred in each direction. This results in an effective full duplex data
rate of 16 kbit/s for the D channel and 64 kbit/s for each B channel.
The final bit of the frame is called the M bit. Its data rate is 4 kbit/s. Four successive
M bits, from four successive U frames, constitute a superframe. Three signals are
carried in this superframe. Every fourth M bit is a code violation (CV) and is used for
superframe synchronization. This can be regarded as the first bit of the superframe.
From this reference (CV = bit 1), bit 3 of the superframe is the service channel bit S. This
TE/PT
LT
t
d
LF
1
U
P0
Interface Frame Structure (= U
B1
8
1)
2)
M Channel Superframe
CV = Code Violation: for Superframe synchronization
T = Transparent Channel (2 kbit/s)
S = Service Channel (1 kbit/s)
DC balancing bit, only sent after a code violation in the
M-bit position and in special configurations.
Timings:
B2
8
t
t
t
t
g
r
d
g
= burst repetition period = 250
= ine delay = 20.8
= guard time = 5.2
t
r
LF-Framing Bit
2-2
99 s
D
4
s
s
PN
maximum
CV T S T CV T S T CV
minimum
)
B1
8
s
t
d
Functional Description
B2
8
PEB 2096
ITD00823
M DC
1 #Bits
1
)
2)
04.99