PEB2096HV31XT Lantiq, PEB2096HV31XT Datasheet - Page 26

• Manufacturer Part Number: PEB2096HV31XT
• Manufacturer: Lantiq

Specifications of PEB2096HV31XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Data Sheet
The PEB 2096, OCTAT-P, covers the electrical requirements of the U
loop lengths depending on the used transformer and the cable quality:
a) If the equalizer is enabled
(EQUDIS in Configuration Register for U
Transformer
2:1
b) If the equalizer is disabled
(EQUDIS in Configuration Register for U
Transformer
2:1
Concerning the 1.25:1 transformer, the maximum line attenuation is decreased by 3 dB.
Note: The actual values of the external resistors depend on the selected transformer.
2.3.2
The transmit PLL (XPLL) synchronizes a 768 kHz transmit clock derived from the
oscillator clock to FSC (8 kHz). When the oscillator clock is synchronous to FSC (fixed
divider ratio of 1920 from 15.36 MHz clock) the XPLL will not perform any tracking after
having locked the phase, i.e. the input jitter on clocks XTAL and FSC will not be
increased.
Alternatively, when a free running oscillator is used, XPLL tracking increases FSC jitter
by 32.5 ns (half oscillator period).
2.3.3
The receive PLL (RPLL) recovers bit timing from a comparator output signal. The
comparator has a threshold of 90 % with respect to the signal stored by the peak
detector. The RPLL performs PLL tracking after detecting phase shifts of the same
polarity in four pulses. A phase adjustment is done by adding or substracting 65 ns (one
oscillator period) to or from the 384 kHz receive clock.
The resistor values in Figure 2-7 and Figure 2-8 are optimal for an ideal
transformer (
Transmit PLL
Receive PLL
R
Cu
= 0).
Cable
AWG 26
Cable
AWG 26
J-Y (ST) Y 2
J-Y (ST) Y 2
PN
PN
2-14
Line Interface is set to low)
Line Interface is set to high)
2
2
0.6
0.6
Loop Length
up to 1 km
up to 1.3 km
Loop Length
up to 0.8 km
up to 1.3 km
Functional Description
PN
interface for
PEB 2096
04.99