PEB2096HV31XT Lantiq, PEB2096HV31XT Datasheet - Page 45

• Manufacturer Part Number: PEB2096HV31XT
• Manufacturer: Lantiq

Specifications of PEB2096HV31XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

INFO 1w and 1/2 are used for initialization and tests. The form of all INFO is shown in
the following table:
Name
INFO 0
INFO 1W
INFO 1
INFO 2
INFO 3
INFO 4
Note:
Data Sheet
1)
2)
F = Framing bit
The M channel superframe contains:
CV code violation
S bits transparent
T bits set to one
DC balancing bit
Direction
Upstream
Downstream
Upstream
Upstream
Downstream 4 kHz burst rate
Upstream
Downstream 4 kHz burst rate
Description
No signal on the line
Asynchronous wake signal
2 kHz burst rate
F0001000100010001000101010100010111111
Code violation in the framing bit (F)
4 kHz burst rate
F000100010001000100010101010001011111M
Code violation in the framing bit with respect to the last
received ’1’
F000100010001000100010101010001011111M
Code violation in the framing bit with respect to the last
transmitted ’1’
4 kHz burst rate
No code violation in the framing bit
User data in B, D and M channels
B channels scrambled, DC bit
No code violation in the framing bit
User data in B, D and M channels
B channels scrambled, DC bit
[1 kbit/s (once in every fourth frame)]
[1 kbit/s channel]
[2 kbit/s channel]
3-17
2)
2
) optional
optional
Operational Description
PEB 2096
1)
1)
DC
04.99
2)