PEB2096HV31XT Lantiq, PEB2096HV31XT Datasheet - Page 31
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PEB2096HV31XT
Manufacturer Part Number
PEB2096HV31XT
Description
Manufacturer
Lantiq
Datasheet
1.PEB2096HV31XT.pdf
(67 pages)
Specifications of PEB2096HV31XT
Control Interface
HDLC
Lead Free Status / Rohs Status
Supplier Unconfirmed
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3.6
There are two possibilities how to synchronize the U
with SSYNC.
3.6.1
The short FSC pulse has a width of one DCL clock (in normal use the FSC is at least 2
DCL wide). The SSYNC input must be set to 1. The period of the short FSC pulses must
be a multiple of 1 ms. The U
channel 0 which follows the short FSC pulse. Refer to Figure 3-2.
•
Figure 3-2
Data Sheet
U
Synchronization with a Short FSC
PN
Synchronization with a short FSC
Multiframe Synchronization
PN
frame with a code violation in the M bit starts in the IOM
3-3
PN
multiframe: With a short FSC or
Operational Description
PEB 2096
04.99
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