PEB2096HV31XT Lantiq, PEB2096HV31XT Datasheet - Page 48

• Manufacturer Part Number: PEB2096HV31XT
• Manufacturer: Lantiq

Specifications of PEB2096HV31XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Data Sheet
4.2
Address:
Format:
Initial Value:
Description:
4.3
Address:
Format:
Initial Value:
Description:
4.4
Test registers are implemented in the address range of 8
customer use.
BEO7
IC7D
bit 7
bit 7
General Configuration Register – (Write)
Bit Error Register – (Read)
Test Registers – (Read/Write)
BEO6
IC6D
1
FF
01
ICnD:
BEM:
1
00
BEOn = 1: Bit error occurred on U
The Bit Error Register is reset after reading the register
H
H
H
H
H
BEO5
IC5D
if the MODE pin is connected to
if the MODE pin is connected to
IOM interface channel n disable (channel 1-7)
0...IOM channel n is enabled
1...IOM channel n is tristated
Bit error mask
0...whenever the Bit Error Register value is unequal to
zero, the register value is transmitted via the monitor
channel
1...the Bit Error Register may be read, but there are no
unsolicited monitor messages
BEO4
IC4D
4-2
BEO3
IC3D
PN
line n.
BEO2
IC2D
H
to B
Registers Description
V
V
DD
SS
BEO1
H
IC1D
; they are not for
or
PEB 2096
BEO0
BEM
bit 0
bit 0
04.99