PEB2096HV31XT Lantiq, PEB2096HV31XT Datasheet - Page 51

• Manufacturer Part Number: PEB2096HV31XT
• Manufacturer: Lantiq

Specifications of PEB2096HV31XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

'HOD\ 5HJLVWHU IRU 8
Address:
Format:
Initial Value:
'(/$<  
Data Sheet
DELAY7
bit7
DELAY6 DELAY5 DELAY4 DELAY3 DELAY2 DELAY1 DELAY0
2
00
Measured delay between U
with a programmed resolution of 65 ns or 130 ns.
The measured value indicates the delay between the transmitted
M bit and the received LF bit minus two bits (the guard time).
In order to evaluate the delay in one direction the measured delay
is divided by two.
After hardware reset, the line delay of transceiver No. 0 is measured
with a resolution of 1 oscillator period. The delay is measured only if
the selected channel is in the state "Activated". The measured delay
is valid if at least 2 U
"Activated". If the selcted transceiver No. was changed by
programming the Configuration Register for U
a new value the new delay is also valid after the receiption of at least
2 U
The transmitter and receiver delays of OCTAT-P
analog path are included in the delay measurement.
H
H
PN
/LQH ,QWHUIDFHV  5HDG
frames.
PN
4-5
frames have been received in the state
PN
transmit and receive frame
Registers Description
PN
Line Interfaces with
PEB 2096
bit0
04.99