N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 110

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Instructions
9.3.6
9.3.7
110/150
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit.
Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and
DQ3, the instruction functionality is exactly the same as the Write Disable (WRDI)
instruction of the Extended SPI protocol, please refer to
(WRDI)
Figure 77. Write Disable instruction sequence QIO-SPI
Quad Command Page Program (QCPP)
The Quad Command Page Program (QCPP) instruction allows to program the memory
content in DIO-SPI protocol, parallelizing the instruction code, the address and the input
data on four pins (DQ0, DQ1, DQ2 and DQ3). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. The Quad Command Page
Program (QCPP) instruction can be issued, when the device is set in QIO-SPI mode, by
sending to the memory indifferently one of the 3 instructions codes: 02h, 12h or 32h, the
effect is exactly the same. The 3 instruction codes are all accepted to help the application
code porting from Extended SPI protocol to QIO-SPI protocol.
Apart for the parallelizing on four pins of the instruction code, the Quad Command Page
Program instruction functionality is exactly the same as the Quad Input Extended Fast
Program of the Extended SPI protocol, please refer to
Fast Program
for further details.
for further details.
DQ0
DQ1
DQ3
DQ2
C
S
Instruction
0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
Quad_Write_Disable
Section 9.1.16: Quad Input Extended
Section 9.1.11: Write Disable
©2010 Micron Technology, Inc. All rights reserved.
N25Q064 - 3 V