N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 32

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Volatile and Non Volatile Registers
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
32/150
Table 2.
WIP bit
The Write In Progress (WIP) bit set to 1 indicates that the memory is busy with a Write
Status Register, Program or Erase cycle. 0 indicates no cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit set to 1 indicates that the internal Write Enable Latch is
set. When set to 0 the internal Write Enable Latch is reset and no Write Status Register,
Program or Erase instruction is accepted.
BP3, BP2, BP1, BP0 bits
The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the
area to be software protected against Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) instruction. When one or more of the Block
Protect (BP3, BP2, BP1, BP0) bits is set to 1, the relevant memory area, as defined in
10.: Protected area sizes (TB bit = 0)
instructions. The Block Protect (BP3, BP2, BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if,
and only if, all Block Protect (BP3, BP2, BP1, BP0) bits are 0.
TB bit
The Top/Bottom (TB) bit is non-volatile. It can be set and reset with the Write Status Register
(WRSR) instruction provided that the Write Enable (WREN) instruction has been issued.
The Top/Bottom (TB) bit is used in conjunction with the Block Protect (BP3, BP2, BP1, BP0)
bits to determine if the protected area defined by the Block Protect bits starts from the top or
the bottom of the memory array:
The TB bit cannot be written when the SRWD bit is set to '1' and the W pin is driven Low.
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and the Write Protect
(W/VPP) signal allow the device to be put in the hardware protected mode (when the Status
Register Write Disable (SRWD) bit is set to '1', and Write Protect ((W/VPP) is driven Low). In
this mode, the non-volatile bits of the Status Register (TB, BP3, BP2, BP1, BP0) become
read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
When TB is reset to '0' (default value), the area protected by the Block Protect bits
starts from the top of the memory array.
When TB is set to '1', the area protected by the Block Protect bits starts from the bottom
of the memory array.
Status register format
becomes protected against all program and erase
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Write enable latch bit
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Write in progress bit
N25Q064 - 3 V
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