N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 80

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Instructions
Table 18.
1. As defined by the values in the Block Protect (TB, BP3, BP2, BP1, BP0) bits of the Status Register, as shown in
9.1.25
80/150
1
0
1
0
W / VPP
Signal
Status register
0
0
1
1
SRWD
bit
Regardless of the order of the two events, the Hardware Protected mode (HPM) can be
entered in either of the following ways:
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W/VPP) High.
If Write Protect (W/VPP) is permanently tied High, the Hardware Protected mode (HPM) can
never be activated, and only the Software Protected mode (SPM), using the Block Protect
(BP3, BP2, BP1, BP0) bits of the Status Register, can be used.
Protection modes
Read Lock Register (RDLR)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any
location inside the concerned sector. Each address bit is latched-in during the rising edge of
Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data output
(DQ1), each bit being shifted out, at a maximum frequency fC, during the falling edge of
Serial Clock (C).
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
format.
setting the Status Register Write Disable (SRWD) bit after driving Write Protect
(W/VPP) Low
driving Write Protect (W/VPP) Low after setting the Status Register Write Disable
(SRWD) bit.
Software
protected
(SPM)
Hardware
protected
(HPM)
Mode
Status register is writeable, if the
WREN instruction has set the WEL
bit.
The values in the SRWD, TB, BP3,
BP2, BP1, and BP0 bits can be
changed.
Status Register is hardware write
protected. The values in the
SRWD, TB, BP3, BP2, BP1 and
BP0 bits cannot be changed
Write protection of the status
register
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Protected against PP,
DIFP, DIEFP, QIFP,
QIEFP, SSE, SE and
BE instructions.
PP, DIFP, DIEFP,
QIFP, QIEFP, SSE,
SE and BE
instructions.
Protected area
Memory content
©2010 Micron Technology, Inc. All rights reserved.
(1)
Ready to accept PP,
DIFP, DIEFP, QIFP,
QIEFP, SSE, and SE
instructions.
PP, DIFP, DIEFP,
QIFP, QIEFP, SSE,
and SE instructions.
Unprotected area
N25Q064 - 3 V
Table 2:
(1)