N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 95

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

N25Q064 - 3 V
9.2.11
9.2.12
DQ0
DQ1
*Address bit A23 is “Don’t Care.”
C
S
Figure 54. Sector Erase instruction sequence DIO-SPI
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed.
Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Bulk Erase (BE) instruction of the
Extended SPI protocol, please refer to
Figure 55. Bulk Erase instruction sequence DIO-SPI
Program/Erase Suspend
The Program/Erase Suspend instruction allows the controller to interrupt a Program or an
Erase instruction, in particular: Sector Erase and Dual Command Page Program can be
suspended and erased while Subsector Erase, Bulk Erase, Write Non Volatile Configuration
register, and Program OTP cannot be suspended.
0
Instruction
S
C
DQ0
1
DQ1
2
3
23 21 19 17
22 20 18 16
4
5
6
Section 9.1.20: Bulk Erase (BE)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
7
Instruction
24-Bit Address*
15 13 11 9
14 12 10 8
1
8
2
9 10 11
Dual_Bulk_Erase
3
12 13 14 15
7
6
©2010 Micron Technology, Inc. All rights reserved.
5
4
3
2
for further details.
1
Dual_S ector_E rase
0
Instructions
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