N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 72

no-image

N25Q064A13EF640F

Manufacturer Part Number
N25Q064A13EF640F
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of N25Q064A13EF640F

Lead Free Status / Rohs Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
N25Q064A13EF640F
Manufacturer:
MICRON
Quantity:
1 001
Part Number:
N25Q064A13EF640F
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
N25Q064A13EF640F
Manufacturer:
MICRON/镁光
Quantity:
20 000
Part Number:
N25Q064A13EF640F
0
Instructions
9.1.17
72/150
DQ0
DQ3
DQ1
DQ2
*Address bit A23 is “Don’t Care. ”
C
S
Figure 25. Quad Input Extended Fast Program instruction sequence
Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded, the device sets the Write Enable Latch (WEL) bit.
The Program OTP instruction is entered by driving Chip Select (S) Low, followed by the
instruction opcode, three address bytes and at least one data byte on Serial Data input
(DQ0). Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Program OTP instruction is not executed.
There is no rollover mechanism with the Program OTP (POTP) instruction. This means that
the Program OTP (POTP) instruction must be sent with a maximum of 65 bytes to program,
once all 65 bytes have been latched in, any following byte will be discarded.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Program OTP cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Program OTP cycle, and it is 0 when it is completed. At
some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is
reset.
Bit 0 of the OTP control byte, that is byte 64, is used to permanently lock the OTP memory
array.
Once a bit of the OTP memory has been programmed to '0', it can no longer be set to '1'.
When bit 0 of byte 64 = '1', the 64 bytes of the OTP memory array can be programmed.
When bit 0 of byte 64 = '0', the 64 bytes of the OTP memory array are read-only and
cannot be programmed anymore.
0
‘1’
Don’t Care
Don’t Care
1
Instruction
2
3
4
5
6
7
23 19 15
20 16 12 8
21 17 13 9
22 18 14 10
8
24-bit address*
9 10
11
11 12 13 14 15 16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
6
7
5
4
3
1
2
0
7
5
6
4
MSB
1
Data In
3
1
2
0
7
5
6
4
MSB
2
17 18 19
2
3
1
0
6
7
5
4
MSB
3
Data In
3
1
2
0
20
©2010 Micron Technology, Inc. All rights reserved.
6
7
5
MSB
4
4
3
21
1
2
0
22
7
5
6
4
MSB
5
Data In
23
3
1
2
0
7
24
5
6
4
MSB
N25Q064 - 3 V
6
25
2
3
1
0
7
26
5
6
4
MSB
7
27
2
3
1
0

Related parts for N25Q064A13EF640F