N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 61

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

N25Q064 - 3 V
9.1.6
DQ0
DQ0
DQ1
DQ1
*Address bit A23 is “Don’t Care.”
C
S
C
S
Mode 3
Mode 2
The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual
Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte,
each bit being latched-in during the rising edge of Serial Clock (C). Then the memory
contents, at that address, are shifted out on DQ0 and DQ1 at a maximum frequency Fc,
during the falling edge of Serial Clock (C).
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out on DQ0 and DQ1. The whole
memory can, therefore, be read with a single Dual Output Fast Read (DOFR) instruction.
When the highest address is reached, the address counter rolls over to 00 0000h, so that
the read sequence can be continued indefinitely.
Figure 14. Dual Output Fast Read instruction sequence
Dual I/O Fast Read
The Dual I/O Fast Read (DIOFR) instruction is very similar to the Dual Output Fast Read
(DOFR), except that the address bits are shifted in on two pins (pin DQ0 and pin DQ1)
instead of only one.
32 33 34
Dummy cycles
0
35
1
36 37 38 39 40 41 42 43 44 45 46
2
Instruction
High Impedance
3
4
MSB
5
6
7
DATA OUT 1
6
4
5
7
2
3
23 22 21
8
0
1
MSB
9 10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
6
7
DATA OUT 2
24-bit address*
4
5
2
3
3
28 29 30 31
0
1
47
2
MSB
6
7
DATA OUT 3
1
4
5
0
2
3
0
1
©2010 Micron Technology, Inc. All rights reserved.
MSB
6
7
DATA OUT n
4
5
2
3
0
1
Instructions
MSB
61/150