N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 129

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

N25Q064 - 3 V
Note:
10.3
DQ0
DQ3
DQ1
DQ2
Xb is the XIP Confirmation bit and should be set as follows: 0 to keep XIP state; 1 to exit XIP mode and return to standard read mode.
*This bit is “Don’t Care.”
C
S
Mode 3
Mode 0
Then after the next de-select and select cycle (S pin set to 1 and then to 0) the memory
codify the first 3 bytes received on the input pin(s) directly as an address, without any
instruction code, and after the dummy clock cycles (configurable) directly outputs the data.
For example to enable the XIP (without enter) with six dummy clock cycles, the pattern in
Table 24.: VCR XIP bits setting example
for example, in XIP mode from extended SPI read mode by mean of Quad Input Output Fast
Read instruction, as described in
For devices with a feature set digit equal to 2 or 4 in the part number (Basic XiP), it is not
necessary to set the Volatile Configuration Register bit 3 to enter in XIP mode: it is possible
to enter directly in XIP mode by setting XIP Confirmation bit to 0 during the first dummy
clock cycle after a fast read instruction. See
Table 24.
Figure 101. XiP: enter by VCR 2/2 (QIOFR in normal SPI protocol example)
XIP mode hold and exit
The XIP mode does require at least one additional clock cycle to allow the XIP Confirmation
bit to be sent to the memory on DQ0 during the first dummy clock cycle.
0
‘1’
Don’t Care
Don’t Care
1
81h (WRVCR opcode)
2
Instruction
VCR XIP bits setting example
3
4
5
6
7
A23-16 A15-8 A7-0
7*
4
5
6
8
2
3
0
1
9 10 11 12 13 14
Table 24.: VCR XIP bits setting
4
5
6
7
2
3
0
1
6
7
4
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
must be issued, and after that it is possible to enter,
6 dummy
+ 0110
cycles
0
1
2
3
Section 16: Ordering
Xb
Dummy (ex.: 6)
15 16
Ready for
17 18
XIP
0
19
20
6
©2010 Micron Technology, Inc. All rights reserved.
7
4
5
Byte 1
example.
information.
IO switches from Input to Output
21
3
1
2
0
22
6
7
4
5
Byte 2
Reserved
23
3
1
2
0
011
XIP Operations
5
6
7
4
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