ADDS-BF533-EZLITE Analog Devices Inc, ADDS-BF533-EZLITE Datasheet - Page 18

• Manufacturer Part Number: ADDS-BF533-EZLITE
• Manufacturer: Analog Devices Inc

Specifications of ADDS-BF533-EZLITE

• Significant Other Parts: ADV7183 Video Decode
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/ADSP-BF532/ADSP-BF533
PIN DESCRIPTIONS
ADSP-BF531/ADSP-BF532/ADSP-BF533 processor pin defini­
tions are listed in
All pins are three-stated during and immediately after reset,
except the memory interface, asynchronous memory control,
and synchronous memory control pins, which are driven high.
Table 9. Pin Descriptions
Pin Name
Memory Interface
Asynchronous Memory Control
Synchronous Memory Control
Timers
PPI Port
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
BR
BG
BGH
AMS3–0
ARDY
AOE
ARE
AWE
SRAS
SCAS
SWE
SCKE
CLKOUT
SA10
SMS
TMR0
TMR1/PPI_FS1
TMR2/PPI_FS2
PPI3–0
PPI_CLK/TMRCLK
Table
9.
Type Function
O
I/O
O
I
O
O
O
I
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I
Address Bus for Async/Sync Access
Bus Request (This pin should be pulled HIGH if not used.)
Bus Grant
Bus Grant Hang
Bank Select
Hardware Ready Control (This pin should be pulled HIGH if not used.)
Output Enable
Read Enable
Write Enable
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Output
A10 Pin
Bank Select
Timer 0
PPI Clock/External Timer Reference
Data Bus for Async/Sync Access
Byte Enables/Data Masks for Async/Sync Access
Timer 1/PPI Frame Sync1
Timer 2/PPI Frame Sync2
PPI3–0
Rev. E | Page 18 of 60 | July 2007
If BR is active, then the memory pins are also three-stated. All
unused I/O pins have their input buffers disabled with the
exception of the pins that need pull-ups or pull-downs as noted
in the table footnotes.
In order to maintain maximum functionality and reduce pack­
age size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate function­
ality is shown in italics.
Driver
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
B
A
A
C
C
C
C
1