ADDS-BF533-EZLITE Analog Devices Inc, ADDS-BF533-EZLITE Datasheet - Page 26

ADDS-BF533-EZLITE

Manufacturer Part Number
ADDS-BF533-EZLITE
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADDS-BF533-EZLITE

Significant Other Parts
ADV7183 Video Decode
Lead Free Status / Rohs Status
Not Compliant
ADSP-BF531/ADSP-BF532/ADSP-BF533
Asynchronous Memory Read Cycle Timing
Table 17. Asynchronous Memory Read Cycle Timing
1
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, ARE.
SDAT
HDAT
SARDY
HARDY
DO
HO
CLKOUT
ADDR19–1
AMSx
ABE1–0
ARE
ARDY
AOE
DATA15–0
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
ARDY Setup Before CLKOUT
ARDY Hold After CLKOUT
Output Delay After CLKOUT
Output Hold After CLKOUT
2 CYCLES
SETUP
t
DO
1
1
Figure 12. Asynchronous Memory Read Cycle Timing
PROGRAMMED READ ACCESS
t
DO
Rev. E | Page 26 of 60 | July 2007
4 CYCLES
t
SARDY
ABE, ADDRESS
t
HARDY
ACCESS EXTENDED
3 CYCLES
Min
2.1
1.0
4.0
1.0
1.0
t
SARDY
V
DDEXT
= 1.8 V
Max
6.0
t
t
HO
SDAT
READ
t
HARDY
1 CYCLE
HOLD
Min
2.1
0.8
4.0
0.0
0.8
V
DDEXT
t
HDAT
= 2.5 V/3.3 V
Max
6.0
t
HO
Unit
ns
ns
ns
ns
ns
ns