ADDS-BF533-EZLITE Analog Devices Inc, ADDS-BF533-EZLITE Datasheet - Page 25

• Manufacturer Part Number: ADDS-BF533-EZLITE
• Manufacturer: Analog Devices Inc

Specifications of ADDS-BF533-EZLITE

• Significant Other Parts: ADV7183 Video Decode
• Lead Free Status / Rohs Status: Not Compliant

Clock and Reset Timing
Table 16
Absolute Maximum Ratings on Page
CLKIN and clock multipliers/divisors must not result in core/
Table 16. Clock and Reset Timing
1
2
3
4
5
Parameter
Timing Requirements
t
t
t
t
Applies to PLL bypass mode and PLL nonbypass mode.
CLKIN frequency must not change on the fly.
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
If the DF bit in the PLL_CTL register is set, then the maximum t
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2,000 CLKIN cycles, while RESET is asserted,
CKIN
CKINL
CKINH
WRST
Table 15 on Page
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
and
CLKIN Period
CLKIN Low Pulse
CLKIN High Pulse
RESET Asserted Pulse Width Low
Figure 11
CLKIN
RESET
24. Since the default behavior of the PLL is to multiply the CLKIN frequency by 10, the 400 MHz speed grade parts cannot use the full CLKIN period range.
describe clock and reset operations. Per
1, 2, 3, 4
t
CKINL
t
CKIN
23, combinations of
t
CKINH
5
CKIN
Rev. E | Page 25 of 60 | July 2007
Figure 11. Clock and Reset Timing
period is 50 ns.
t
WRST
ADSP-BF531/ADSP-BF532/ADSP-BF533
system clocks exceeding the maximum limits allowed for the
processor, including system clock restrictions related to supply
voltage.
VCO
, f
CCLK
, and f
SCLK
Min
25.0
10.0
10.0
11 t
settings discussed in
CKIN
Table 12 on Page 24
Max
100.0
through
Unit
ns
ns
ns
ns