ADDS-BF533-EZLITE Analog Devices Inc, ADDS-BF533-EZLITE Datasheet - Page 28

ADDS-BF533-EZLITE

Manufacturer Part Number
ADDS-BF533-EZLITE
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADDS-BF533-EZLITE

Significant Other Parts
ADV7183 Video Decode
Lead Free Status / Rohs Status
Not Compliant
ADSP-BF531/ADSP-BF532/ADSP-BF533
SDRAM Interface Timing
Table 19. SDRAM Interface Timing
1
2
3
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
SDRAM timing for T
Refer to
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
SSDAT
HSDAT
SCLK
SCLKH
SCLKL
DCAD
HCAD
DSDAT
ENSDAT
Table 15 on Page 24
DATA Setup Before CLKOUT
DATA Hold After CLKOUT
CLKOUT Period
CLKOUT Width High
CLKOUT Width Low
Command, ADDR, Data Delay After CLKOUT
Command, ADDR, Data Hold After CLKOUT
Data Disable After CLKOUT
Data Enable After CLKOUT
JUNCTION
CMND ADDR
DATA(OUT)
= 125°C is limited to 100 MHz.
(OUT)
DATA(IN)
for maximum f
CLKOUT
2
SCLK
1
at various V
t
SSDAT
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
DDINT
.
Rev. E | Page 28 of 60 | July 2007
1
3
Figure 14. SDRAM Interface Timing
t
DCAD
t
SCLK
t
t
ENSDAT
H SDAT
t
t
DC AD
HCAD
t
SCLKL
Min
2.1
0.8
10.0
2.5
2.5
1.0
1.0
V
DDEXT
t
t
DSDAT
SCLKH
= 1.8 V
Max
6.0
6.0
t
HCAD
Min
1.5
0.8
7.5
2.5
2.5
1.0
1.0
V
DDEXT
= 2.5 V/3.3 V
Max
4.0
4.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns