ADDS-BF533-EZLITE Analog Devices Inc, ADDS-BF533-EZLITE Datasheet - Page 24

• Manufacturer Part Number: ADDS-BF533-EZLITE
• Manufacturer: Analog Devices Inc

Specifications of ADDS-BF533-EZLITE

• Significant Other Parts: ADV7183 Video Decode
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/ADSP-BF532/ADSP-BF533
TIMING SPECIFICATIONS
Table 12
the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor clocks.
Take care in selecting MSEL, SSEL, and CSEL ratios so as not to
exceed the maximum core clock and system clock as described
Table 12. Core Clock (CCLK) Requirements—400 MHz Models
1
2
Table 13. Core Clock (CCLK) Requirements—500 MHz, 533 MHz, and 600 MHz Models
1
2
3
Table 14. Phase-Locked Loop Operating Conditions
Table 15. System Clock (SCLK) Requirements
1
Parameter
f
f
f
f
f
Parameter
f
f
f
f
f
f
f
Parameter
f
Parameter
MBGA/PBGA
f
f
LQFP
f
f
See
See
Applies to 600 MHz models only. See
Applies to 533 MHz and 600 MHz models only. See
Applies to 500 MHz, 533 MHz, and 600 MHz models. See
t
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
VCO
SCLK
SCLK
SCLK
SCLK
SCLK
Ordering Guide on Page
Operating Conditions on Page
(= 1/f
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
Voltage Controlled Oscillator (VCO) Frequency
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
SCLK
through
) must be greater than or equal to t
1
Table 15
CLKOUT/SCLK Frequency (V
CLKOUT/SCLK Frequency (V
CLKOUT/SCLK Frequency (V
CLKOUT/SCLK Frequency (V
59.
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
describe the timing requirements for
21.
=1.14 V Minimum)
=1.045 V Minimum)
=0.95 V Minimum)
=0.85 V Minimum)
=0.8 V Minimum)
=1.3 V Minimum)
=1.2 V Minimum)
=1.14 V Minimum)
=1.045 V Minimum)
=0.95 V Minimum)
=0.85 V Minimum)
=0.8 V Minimum)
Ordering Guide on Page
CCLK
.
Ordering Guide on Page
Ordering Guide on Page
1
2
3
DDINT
DDINT
DDINT
DDINT
59.
≥ 1.14 V)
< 1.14 V)
≥ 1.14 V)
< 1.14 V)
Rev. E | Page 24 of 60 | July 2007
Internal Regulator Setting
Internal Regulator Setting
59. 533 MHz models cannot support internal regulator levels above 1.25 V.
1.20 V
1.10 V
1.00 V
0.90 V
0.85 V
1.30 V
1.25 V
1.20 V
1.10 V
1.00 V
0.90 V
0.85 V
1
59. 500 MHz models cannot support internal regulator levels above 1.20 V.
in
trolled oscillator (VCO) operating frequencies described in
Table
conditions.
Absolute Maximum Ratings on Page
14.
Table 14
V
T
Min
DDEXT
JUNCTION
50
Max
100
100
100
83
describes phase-locked loop operating
Max
400
333
295
= 1.8 V
= 125°C
Maximum f
V
DDEXT
Max
600
533
500
444
400
333
250
All
Max
2
23, and the voltage con­
Other T
= 2.5 V/3.3 V
Max
133
100
133
83
Max
400
364
333
280
250
CCLK
JUNCTION
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
MHz
Unit
MHz
MHz
MHz
MHz
MHz
Unit
MHz
MHz
MHz
MHz