ADDS-BF533-EZLITE Analog Devices Inc, ADDS-BF533-EZLITE Datasheet - Page 29

• Manufacturer Part Number: ADDS-BF533-EZLITE
• Manufacturer: Analog Devices Inc

Specifications of ADDS-BF533-EZLITE

• Significant Other Parts: ADV7183 Video Decode
• Lead Free Status / Rohs Status: Not Compliant

External Port Bus Request and Grant Cycle Timing
Table 20
bus grant operations.
Table 20. External Port Bus Request and Grant Cycle Timing
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
BS
BH
SD
SE
DBG
EBG
DBH
EBH
BR Asserted to CLKOUT High Setup
CLKOUT High to BR Deasserted Hold Time
CLKOUT Low to AMSx, Address, and ARE/AWE Disable
CLKOUT Low to AMSx, Address, and ARE/AWE Enable
CLKOUT High to BG High Setup
CLKOUT High to BG Deasserted Hold Time
CLKOUT High to BGH High Setup
CLKOUT High to BGH Deasserted Hold Time
and
CLKOUT
ADDR19-1
Figure 15
ABE1-0
AMSx
AWE
BGH
ARE
BR
BG
describe external port bus request and
t
BS
Figure 15. External Port Bus Request and Grant Cycle Timing
t
Rev. E | Page 29 of 60 | July 2007
BH
Min
4.6
1.0
LQFP/PBGA Packages
ADSP-BF531/ADSP-BF532/ADSP-BF533
V
DDEXT
t
t
t
SD
SD
SD
= 1.8 V
Max
4.5
4.5
6.0
6.0
6.0
6.0
t
t
DBG
DBH
Min
4.6
1.0
MBGA Package
V
DDEXT
= 1.8 V
Max
4.5
4.5
4.6
4.6
4.6
4.6
t
t
Min
4.6
0.0
V
EBG
EBH
DDEXT
All Packages
= 2.5 V/3.3 V
t
t
t
SE
SE
SE
Max
4.5
4.5
3.6
3.6
3.6
3.6
Unit
ns
ns
ns
ns
ns
ns
ns
ns