ADDS-BF533-EZLITE Analog Devices Inc, ADDS-BF533-EZLITE Datasheet - Page 30

• Manufacturer Part Number: ADDS-BF533-EZLITE
• Manufacturer: Analog Devices Inc

Specifications of ADDS-BF533-EZLITE

• Significant Other Parts: ADV7183 Video Decode
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/ADSP-BF532/ADSP-BF533
Parallel Peripheral Interface Timing
Table 21
parallel peripheral interface operations.
Table 21. Parallel Peripheral Interface Timing
1
2
3
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics—GP Output and Frame Capture Modes
t
t
t
t
PPI_CLK frequency cannot exceed f
Applies when PPI_CONTROL Bit 8 is cleared. See
Applies when PPI_CONTROL Bit 8 is set. See
PCLKW
PCLK
SFSPE
HFSPE
SDRPE
HDRPE
DFSPE
HOFSPE
DDTPE
HDTPE
POLC = 0
PPI_CLK
PPI_CLK
POLC = 1
PPI_FS1
PPI_FS2
PPI_DATA
PPI_CLK Width
PPI_CLK Period
External Frame Sync Setup Before PPI_CLK Edge
(Nonsampling Edge for Rx, Sampling Edge for Tx)
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
and
POLS = 1
POLS = 0
POLS = 1
POLS = 0
Figure 16
1
through
SCLK
/2
Figure 21 on Page 33
Figure 18 on Page 31
Figure 17 on Page 31
Figure 16. PPI GP Rx Mode with Internal Frame Sync Timing
t
HOFSPE
FRAME
SYNC IS
DRIVEN
OUT
t
Rev. E | Page 30 of 60 | July 2007
DFSPE
describe
t
and
SDRPE
and
Figure 21 on Page
DATA0
IS
SAMPLED
Figure 20 on Page
t
HDRPE
1.5
Min
8.0
20.0
6.0
1.0
2.0
3.5
1.7
1.8
LQFP/PBGA Packages
2
3
V
DDEXT
33.
= 1.8 V
Max
11.0
11.0
32.
Min
8.0
20.0
6.0
1.0
2.0
3.5
1.5
1.7
1.8
MBGA Package
V
2
3
DDEXT
= 1.8 V
Max
8.0
9.0
1.5
V
Min
6.0
15.0
4.0
6.0
1.0
2.0
3.5
1.7
1.8
DDEXT
2
3
2
3
All Packages
= 2.5 V/3.3 V
Max
8.0
9.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns