ADDS-BF533-EZLITE Analog Devices Inc, ADDS-BF533-EZLITE Datasheet - Page 42

• Manufacturer Part Number: ADDS-BF533-EZLITE
• Manufacturer: Analog Devices Inc

Specifications of ADDS-BF533-EZLITE

• Significant Other Parts: ADV7183 Video Decode
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/ADSP-BF532/ADSP-BF533
JTAG Test and Emulation Port Timing
Table 30
Table 30. JTAG Port Timing
1
2
3
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs = DATA15–0, ARDY, TMR2–0, PF15–0, PPI_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
50 MHz maximum
System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2–0, PF15–0, RSCLK0–1, RFS0–1,
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
RESET, NMI, BMODE1–0, BR, PP3–0.
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3–0.
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse Width
TDO Delay from TCK Low
System Outputs Delay After TCK Low
and
SYSTEM
TCK
TMS
TDO
TDI
INPUTS
SYSTEM
OUTPUT
Figure 29
describe JTAG port operations.
2
(Measured in TCK Cycles)
t
DSYS
t
DTDO
1
t
SSYS
3
1
t
STAP
Rev. E | Page 42 of 60 | July 2007
t
TCK
Figure 29. JTAG Port Timing
t
HSYS
t
HTAP
Min
20
4
4
4
5
4
0
V
DDEXT
= 1.8 V
Max
10
12
V
Min
20
4
4
4
5
4
0
DDEXT
= 2.5 V/3.3 V
Max
10
12
Unit
ns
ns
ns
ns
ns
TCK
ns
ns