ADDS-BF533-EZLITE Analog Devices Inc, ADDS-BF533-EZLITE Datasheet - Page 34

• Manufacturer Part Number: ADDS-BF533-EZLITE
• Manufacturer: Analog Devices Inc

Specifications of ADDS-BF533-EZLITE

• Significant Other Parts: ADV7183 Video Decode
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Ports
Table 22
through
Table 22. Serial Ports—External Clock
1
2
3
Table 23. Serial Ports—Internal Clock
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
Referenced to sample edge.
For receive mode with external RSCLKx and external RFSx only, the maximum specification is 11.11 ns (90 MHz).
Referenced to drive edge.
Referenced to sample edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKEW
SCLKE
DFSE
HOFSE
DDTE
HDTE
SFSI
HFSI
SDRI
HDRI
SCLKEW
SCLKE
DFSI
HOFSI
DDTI
HDTI
SCLKIW
TFSx/RFSx Setup Before TSCLKx/RSCLKx
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
TSCLKx/RSCLKx Width
TSCLKx/RSCLKx Period
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
TSCLKx/RSCLKx Width
TFSx/RFSx Setup Before TSCLKx/RSCLKx
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
TSCLKx/RSCLKx Width
TSCLKx/RSCLKx Period
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
Figure 23 on Page 36
through
Table 25 on Page 35
describe Serial Port operations.
1
1
and
1
1
1
1
1
1
Figure 22 on Page 35
1
1
1
1
Rev. E | Page 34 of 60 | July 2007
2
1
Min
11.0
−2.0
9.5
0.0
4.5
20.0
−1.0
−2.5
6.0
1
3
V
LQFP/PBGA
DDEXT
Packages
= 1.8 V
Max
3.0
3.0
Min
3.0
3.0
3.0
3.0
8.0
20.0
0.0
0.0
Min
11.0
−2.0
9.0
0.0
4.5
15.0
−1.0
−2.0
6.0
V
MBGA Package
V
DDEXT
DDEXT
= 1.8 V
Max
10.0
10.0
= 1.8 V
Max
3.0
3.0
Min
3.0
3.0
3.0
3.0
4.5
15.0
0.0
0.0
V
Min
9.0
−2.0
9.0
0.0
4.5
15.0
−1.0
−2.0
4.5
V
DDEXT
DDEXT
All Packages
2
= 2.5 V/3.3 V
= 2.5 V/3.3 V
Max
10.0
10.0
Max
3.0
3.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns