ADDS-BF533-EZLITE Analog Devices Inc, ADDS-BF533-EZLITE Datasheet - Page 37

• Manufacturer Part Number: ADDS-BF533-EZLITE
• Manufacturer: Analog Devices Inc

Specifications of ADDS-BF533-EZLITE

• Significant Other Parts: ADV7183 Video Decode
• Lead Free Status / Rohs Status: Not Compliant

Serial Peripheral Interface (SPI) Port
—Master Timing
Table 26
Table 26. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
SSPIDM
SDSCIM
SPICHM
SPICLM
SPICLK
HDSM
SPITDM
DDSPIDM
HDSPIDM
HSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
SPISELx Low to First SCK Edge
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISELx High
Sequential Transfer Delay
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
CPHA = 0
CPHA = 1
and
Figure 24
(OUTPUT)
(INPUT)
(INPUT)
(OUTPUT)
(OUTPUT)
(CPOL = 0)
(CPOL = 1)
SPISELx
(OUTPUT)
(OUTPUT)
MISO
MISO
MOSI
MOSI
SCK
SCK
describe SPI port master operations.
t
SSPIDM
t
SDSCIM
MSB VALID
t
SSPIDM
Figure 24. Serial Peripheral Interface (SPI) Port—Master Timing
MSB
t
t
SPICHM
SPICLM
MSB VALID
t
HSPIDM
t
t
t
DDSPIDM
Rev. E | Page 37 of 60 | July 2007
MSB
SPICLM
SPICHM
Min
10.5
–1.5
2t
2t
2t
4t
2t
2t
0
–1.0
t
HSPIDM
LQFP/PBGA Packages
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
t
DDSPIDM
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
V
DDEXT
= 1.8 V
ADSP-BF531/ADSP-BF532/ADSP-BF533
Max
6
+4.0
t
HDSPIDM
LSB VALID
t
t
SSPIDM
SPICLK
Min
8.5
–1.5
2t
2t
2t
4t
2t
2t
0
–1.0
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
MBGA Package
t
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
HDSPIDM
V
LSB VALID
LSB
DDEXT
= 1.8 V
t
HDSM
LSB
t
HSPIDM
Max
6
+4.0
t
SPITDM
Min
7.5
–1.5
2t
2t
2t
4t
2t
2t
0
–1.0
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
V
DDEXT
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
All Packages
= 2.5 V/3.3 V
Max
6
+4.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns