AS4C8M16S-7TCN ALLIANCE MEMORY, AS4C8M16S-7TCN Datasheet - Page 9

• Manufacturer Part Number: AS4C8M16S-7TCN
• Description: DRAM 128M SDRAM 8M X 16 143MHz
• Manufacturer: ALLIANCE MEMORY

Specifications of AS4C8M16S-7TCN

• Data Bus Width: 16 bit
• Organization: 8 M x 16
• Package / Case: TSOP II-54
• Memory Size: 128 Mbit
• Maximum Clock Frequency: 143 MHz
• Access Time: 5.4 ns, 6 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 130 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Details

5
6
FEBRUARY 2011
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "H", A0-A8 = Column Address)
the read operation. Once this command is given, any subsequent command cannot occur within a
time delay of {t
this command and the auto precharge function is ignored.
(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A8 = Column Address)
row in an active bank. The bank must be active for at least t
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
Write command
t
t
CLK
DQ
COMMAND
CAS# latency=2
CAS# latency=3
COMMAND
CLK
ADDRESS
CK2,
CK3,
The Read and AutoPrecharge command automatically performs the precharge operation after
The Write command is used to write a burst of data on consecutive clock cycles from an active
A write burst without the auto precharge function may be interrupted by a subsequent Write,
DQ
DQ
RP
Figure 10. Burst Write Operation
Figure 9. Read to Precharge
(min.) + burst length}. At full-page burst, only the read operation is performed in
T0
NOP
READ A
T0
Bank,
Col A
are registered on the same clock edge
The first data element and the write
WRITE A
T1
DIN A
T1
NOP
0
T2
DIN A
DOUT A
NOP
T2
NOP
1
0
T3
DOUT A
DOUT A
DIN A
T3
NOP
NOP
9
2
0
1
T4
DOUT A
DOUT A
Precharge
Bank(s)
T4
NOP
DIN A
(CAS# Latency = 2, 3)
3
2
1
(Burst Length = 4)
T5
DOUT A
RCD
DOUT A
don’t care
T5
NOP
NOP
tRP
(min.) before the Write command is
3
2
T6
DOUT A
T6
NOP
NOP
3
Don’t Care
T7
T7
Activate
NOP
Bank
Row
AS4C8M16S
T8
T8
NOP
NOP