AS4C8M16S-7TCN ALLIANCE MEMORY, AS4C8M16S-7TCN Datasheet - Page 25

• Manufacturer Part Number: AS4C8M16S-7TCN
• Description: DRAM 128M SDRAM 8M X 16 143MHz
• Manufacturer: ALLIANCE MEMORY

Specifications of AS4C8M16S-7TCN

• Data Bus Width: 16 bit
• Organization: 8 M x 16
• Package / Case: TSOP II-54
• Memory Size: 128 Mbit
• Maximum Clock Frequency: 143 MHz
• Access Time: 5.4 ns, 6 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 130 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Details

Figure 23. Self Refresh Entry & Exit Cycle
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
4. Once the device enters SelfRefresh mode, minimum t
5. System clock restart and be stable before returning CKE high.
6. Enable CKE and CKE should be set high for valid setup time and hold time.
7. CS# starts from high.
8. Minimum t
9. 4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
CLK
CKE
CS#
RAS#
CAS#
A0-A9,
A11
WE#
BA0,1
DQM
DQ
To Exit SelfRefresh Mode
system uses burst refresh.
FEBRUARY 2011
T0
T1
*Note 1
XSR
Self Refresh Entry
t
IS
is required after CKE going high to complete SelfRefresh exit.
T2
Hi-Z
*Note 2
T3
T4
T5
T6
*Note 3, 4
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
25
Hi-Z
*Note 5
RAS
Self Refresh Exit
*Note 6
is required before exit from SelfRefresh.
*Note 7
t
IS
t
IH
t
XSR
*Note 8
Auto Refresh
t
PDE
*Note 9
Don’t Care
AS4C8M16S