AS4C8M16S-7TCN ALLIANCE MEMORY, AS4C8M16S-7TCN Datasheet - Page 15

• Manufacturer Part Number: AS4C8M16S-7TCN
• Description: DRAM 128M SDRAM 8M X 16 143MHz
• Manufacturer: ALLIANCE MEMORY

Specifications of AS4C8M16S-7TCN

• Data Bus Width: 16 bit
• Organization: 8 M x 16
• Package / Case: TSOP II-54
• Memory Size: 128 Mbit
• Maximum Clock Frequency: 143 MHz
• Access Time: 5.4 ns, 6 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 130 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Details

12 AutoRefresh command
13 SelfRefresh Entry command
11
FEBRUARY 2011
Figure 16. Termination of a Burst Read Operation
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar
to the No Operation command.
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "H", A11 = “Don‘t care, A0-A9 = Don't care)
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
operation must be performed 4096 times within 64ms. The time required to complete the auto
refresh operation is specified by t
be in the idle state and the device must not be in power down mode (CKE is high in the previous
cycle). This command must be followed by NOPs until the auto refresh operation is completed. The
precharge time requirement, t
performed.
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A9 = Don't care)
mode for data retention and low power operation. Once the SelfRefresh command is registered, all
the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW.
The refresh addressing and timing is internally generated to reduce power consumption. The
SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by
restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).
Device Deselect command (CS# = "H")
COMMAND
t
t
CLK
CAS# latency=2
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh
CK2,
CAS# latency=3
CK3,
CLK
COMMAND
DQ
Figure 17. Termination of a Burst Write Operation
DQ
DQ
READ A
T0
T0
NOP
WRITE A
DIN A
T1
T1
NOP
RP
(min), must be met before successive auto refresh operations are
0
RC
(min.). To provide the AutoRefresh command, all banks need to
DIN A
DOUT A
T2
T2
NOP
NOP
1
0
DOUT A
DOUT A
DIN A
T3
T3
NOP
NOP
15
The burst ends after a delay equal to the CAS# latency
2
0
1
DOUT A
DOUT A
T4
Burst Stop
Burst Stop
T4
don’t care
1
2
DOUT A
DOUT A
T5
T5
(Burst Length ＞ 4, CAS# Latency = 2, 3)
NOP
NOP
2
3
DOUT A
T6
T6
NOP
NOP
(Burst Length = X)
3
T7
T7
NOP
NOP
T8
NOP
T8
AS4C8M16S
NOP