AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 199

• Manufacturer Part Number: AT32UC3A4128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 15-22. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Two Read Accesses on Dif-
Figure 15-23. TDF Optimization Disabled (MODE.TDFMODE= 0). TDF Wait States between a Read and a Write Access
32072G–11/2011
Read2 controlling
Write2 controlling
Read1 controlling
Read1 controlling
A[AD_MSB:2]
NBS0, NBS1,
signal(NWE)
signal(NRD)
signal(NRD)
A[AD_MSB:2]
signal(NRD)
A0, A1
NBS0, NBS1,
CLK_SMC
D[15:0]
A0, A1
CLK_SMC
D[15:0]
ferent Chip Selects.
on Different Chip Selects.
TDFCYCLES = 6
with no TDF optimization.
Read1 cycle
• read access followed by a write access on the same chip select.
TDFCYCLES = 4
Read1 cycle
Read1 hold = 1
Read1 hold = 1
Chip Select Wait State
TDFCYCLES = 4
Read to Write
Wait State
TDFCYCLES = 6
Chip Select
Wait State
2 TDF WAIT STATES
5 TDF WAIT STATES
Write2 setup = 1
(optimization disabled)
TDFMODE=0
Write 2 cycle
(optimization disabled)
Read2 setup = 1
TDFMODE=0
Read 2 cycle
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