AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 376

• Manufacturer Part Number: AT32UC3A4128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.12.23 DMA Channel Enable Register
Name:
Access Type:
Offset:
Reset Value:
• CH_EN_WE[11:8]: Channel Enable Write Enable
The channel enable bit, CH_EN, is only written if the corresponding channel write enable bit, CH_EN_WE, is asserted on
the same System Bus write transfer.
For example, writing 0x101 writes a 1 into ChEnReg[0], while ChEnReg[7:1] remains unchanged.
• CH_EN[3:0]
Enables/Disables the channel. Setting this bit enables a channel, clearing this bit disables the channel.
The ChEnReg.CH_EN bit is automatically cleared by hardware to disable the channel after the last System Bus transfer of
the DMA transfer to the destination has completed.Software can therefore poll this bit to determine when a DMA transfer
has completed.
32072G–11/2011
31
23
15
7
-
-
-
-
0 = Disable the Channel
1 = Enable the Channel
30
22
14
6
-
-
-
-
ChEnReg
Read/Write
0x3A0
0x00000000
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
CH_EN_WE
CH_EN3
27
19
11
3
3
-
-
CH_EN_WE
CH_EN2
26
18
10
2
2
-
-
CH_EN_WE
CH_EN1
25
17
9
1
1
-
-
CH_EN_WE
CH_EN0
24
16
8
0
0
-
-
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