AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 342

• Manufacturer Part Number: AT32UC3A4128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.10.1.6
32072G–11/2011
Multi-block DMA Transfer with Linked List for Source and Contiguous Destination Address (Row 8)
Figure 19-16. DMA Transfer for Source Address Auto-reloaded and Contiguous Destination
DMAC Transfer Complete
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the linked list in memory. Write the control information in the LLI. CTLx register
interrupt generated here
location of the block descriptor for each LLI in memory for channel x. For example, in
the register, you can program the following:
a. Set up the transfer type (memory or non-memory peripheral for source and desti-
b. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_TR_WIDTH field.
– ii. Transfer width for the destination in the DST_TR_WIDTH field.
– iii. Source master layer in the SMS field where source resides.
– iv. Destination master layer in the DMS field where destination resides.
nation) and flow control device by programming the TT_FC of the CTLx register.
Address
Channel Disabled by
Block Complete interrupt
hardware
generated here
yes
interrupt cleared by software
DMAC State Machine Table?
Stall until Block Complete
MASKBLOCK[x]=1?
Channel Enabled by
Reload SARx, CTLx
Is DMAC in Row1 of
CTLx.INT_EN=1
Block Transfer
software
&&
no
yes
no
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